With recent variation, size reduction and thinning of electronic components, electronic devices and so on, multilayer printed wiring boards used in them have been size-reduced and thinned, and various configurations have thus been developed. In general, a multilayer printed wiring board is manufactured by forming a circuit in a double-sided metal-foil clad laminated board by a method such as etching, laminating an insulating resin layer, forming a circuit on the surface of the insulating resin layer and further laminating an insulating resin layer, and manufactured by alternately laminating circuits and insulating resin layers.
A double-sided metal-foil clad laminated board is generally formed by impregnating a base material such as a glass cloth with, for example, a thermosetting resin such as an epoxy resin and a phenol resin by immersion to form an insulating layer called as a prepreg and laminating metal foils such as copper foils on both sides of the prepreg or of both sides of multiple laminated prepregs, and the laminate is heated and pressed.
Following such a trend of thinning of a multilayer printed wiring board, there has been investigated thinning or eliminating a prepreg in a double-sided metal-foil clad laminated board.
However, when a semiconductor device is manufactured using a thin multilayer printed wiring board, a connection between a semiconductor element and the multilayer printed wiring board may be subjected to stress due to a difference in linear thermal expansion, which may adversely affect reliability of a semiconductor device. Therefore, a resin composition used in an insulating resin layer in a prepreg or multilayer printed wiring board must have a low expansion coefficient. A resin composition generally contains an epoxy resin, and an expansion coefficient of the resin composition is reduced by adding an inorganic filler and a cyanate resin to the resin composition containing an epoxy resin.
Patent Reference No. 1: Japanese published unexamined application No. 2003-64198.
Patent Reference No. 2: Japanese published unexamined application No. 2002-305374.
Patent Reference No. 3: Japanese published unexamined application No. 2002-299834.
Patent Reference No. 4: Japanese published unexamined application No. 2003-128928.
Patent Reference No. 5: Japanese published unexamined application No. 2006-274236.